MAVISS Strengths
Our strength lies in the fact that we have many semiconductor engineers with over 15 years of design experience at major semiconductor manufacturers, and our technical capabilities backed up by their extensive experience enable us to handle advanced processes and multiple fabs.
To date, we have experience with 7-5 nm processes and five fabs.
In addition, we have made an informal decision to take on the challenge of supporting the 3nm process in FY2024, and we will continue to expand the area of support for cutting-edge processes.
With our ability to propose solutions to problems, our design capability to realize our proposals, and our industry-leading design quality, we will create highly reliable semiconductor products that meet the needs of our customers through OneTeam's pursuit of cutting-edge processes.
We are a virtual design partner (VDP) of Samsung Electronics' foundry business [SAFE™ (Samsung Advanced Foundry Ecosystem)], which is one of only three companies in Japan.
We provide our customers with a wide range of high-quality design services from specification to GDS-II through and through.
Alliance Partners
We cooperate with alliance partners in different fields, both overall and in specific areas of commissioned design, to build a development system that can respond to a variety of customer issues.
commissioned design services
Have you ever had trouble with the initial process of defining requirements when consulting with an external contractor?
Based on our ability to communicate with our customers, we conduct rigorous requirement definition to uncover requirements that are not yet apparent or verbalized, and provide innovative and efficient semiconductor design solutions in a single package.
commissioned design services : ASIC/ASSP
We are able to provide one-stop services from specification identification to design/verification, physical implementation, and actual device verification, backed by our abundant experience and skilled elemental technologies.
We provide strong support for our customers to reduce the risk of backtracking in design and provide more competitive products to the market in a timely manner by designing and implementing solutions with an awareness of overall optimization for complex and compound issues that cannot be solved by individual elemental technologies alone in all processes, including DFT implementation.
commissioned design services : FPGA
Our strength lies in our technical capabilities to maximize the performance of high-end FPGAs, such as optimal function partitioning and function allocation cultivated through SoC design, and various design achievements (realization of high-performance image processing systems) based on large-scale, high-speed design layout technology.
We flexibly respond to our customers' business models with optimal solutions and advanced technical capabilities.
Process scheme
In front-end design, including the definition of requirements as the core of the design, identifying and correcting problems is an important part of the product development process, but it is also a very burdensome process for the client, including management between processes that span multiple companies.
However, we are able to provide a one-stop service from system design, design and verification to the creation of instructions for the physical implementation process, enabling "through and through" development with no feedback loss in consideration of subsequent processes.
We also provide functional evaluation of ES.
Through the entire design and verification process, we propose and design the optimum chip configuration (system controller, CPU subsystem, BUS subsystem, and each functional module) and provide functional and performance verification in order to draw out the customer's potential requirements and realize "the kind of function I want to implement".
In our physical implementation process, our skilled designers, who have developed more than 100 products in Japan and overseas in various fields such as telecommunications, industry (FA/OA), and home appliances, optimize design efficiency by coordinating design processes in response to design details defined at the front end.
Especially in the physical implementation process, as shown in the table below, we can handle the world's most advanced 3nm process to legacy processes at the world's major fabs.
We provide optimal hierarchy proposals based on our advanced understanding of circuit configuration, DFT and timing specifications, and the highest level of layout technology to realize large, high-speed, and low-power SoCs, and provide the optimal process for each customer's business model.
Design Consulting
We also provide the following consulting services for "semiconductor design" to our customers.
Design specification development and refinement:
We clearly define design specifications and refine product requirements based on customer requirements.
Advising and recommendations:
We provide technical advice and propose optimal design strategies and solutions to our clients.
Lectures and support on verification methodologies:
We introduce appropriate verification methodologies and provide lectures and support on the verification process to our clients.
The above is just one example of what we can do.
We specialize in integrated verification and consulting services for the entire process, but we can also provide partial or specific process consultations depending on your needs.
Please feel free to contact us using the inquiry form.
List of tools used
We have experience in designing with many design tools.
| Tool | Bender |
|---|---|
| Conformal (Equivalence check/LowPower/ECO) | Cadence |
| JasperGold (CSR/FPV/CONN/SEC) | Cadence |
| Xcelium | Cadence |
| Palladium | Cadence |
| Quantus QRC | Cadence |
| Genus (RTL compiler) | Cadence |
| Spectre | Cadence |
| Tempus (ETS) | Cadence |
| Virtuoso | Cadence |
| Voltus (Voltage Storm) | Cadence |
| Innovus | Cadence |
| Pegasus | Cadence |
| Design Compiler | Synopsys |
| DFTMAX | Synopsys |
| Formality | Synopsys |
| HSPICE | Synopsys |
| IC Compiler / IC Compiler II | Synopsys |
| PrimeTime / PrimeTime-SI | Synopsys |
| StarRC | Synopsys |
| SpyGlass | Synopsys |
| TetraMAX | Synopsys |
| VCS | Synopsys |
| Verdi | Synopsys |
| Laker | Synopsys |
| IC Validator | Synopsys |
| Calibre / Calibre Inroute | Siemens |
| Questa(ModelSim) | Siemens |
| Olympus-Soc | Siemens |
| Tessent | Siemens |
| Vivado | AMD |
| Quartus | Intel |
Works
Many tape-outs for ASIC (SoC) products for industrial and consumer applications from major semiconductor manufacturers,
both domestic and overseas.
We have experience in design support for all processes from specification design to layout design.
We provide a verification environment tailored to customer needs, including system design such as bus construction and CPU peripheral block integration, logic design and verification, and verification IP to simplify verification and shorten TAT.
DFT implementation, including DFT specification construction for DFT integration of various IPs and optimization of overall fault detection.
Timing design and verification (STA) for timing optimization with emphasis on clock design, including high-speed IFs such as DDR and LVDS
Layout design technology to achieve the world's smallest area, lowest power, and highest speed
The above is just one example of what we can do.
We specialize in integrated verification and consulting services for the entire process, but we can also provide partial or specific process consultations depending on your needs.
Please feel free to contact us using the inquiry form.
Extensive experience in designing functional IP such as memory controllers and CPU peripheral macros
IP design assets that take into account the specifications of higher-level designs (subsystems, single chips)
Custom design and layout optimization considering the above hierarchy (module, 1-chip)
CONTACT
If you have any questions or inquiries about our semiconductor designs or need more information about our services, please call us or use the contact form below.
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