One-chip functional verification environment construction
Customer
A domestic semiconductor manufacturer
End-customer
A domestic Set Manufacturer
Business form
Commissioned design
Scope of business
One-chip functional verification environment construction
Equipped IPs
Cortex-A57, Cortex-M3, ARM926, DDR3L/4, USB2.0H, USB3.0H,USB3.0D,PCIe, SATA, SD, BbyOne, ADC, GEtherMac,GPU
Development time
1.5 months
We provide a verification environment that meets the needs of our customers, including a verification environment using models and shorter TATs.
It is possible to replace the installed IP such as CPU with the bus model. It has the following benefits
- It is possible to perform simple verification of bus access without knowing about IP.
- By changing to a model, the CPU execution load of the simulation can be reduced.
- Total management from SIM execution to result confirmation by supporting vMavager (Cadence).