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FED design example

Front-end design example 1

Business Overview
	Customers	Domestic semiconductor manufacturers
	End customers	Domestic set manufacturers
	Business form	Design outsourcing services
	Scope of work	Chip functional verification environment construction
Product Overview
	Equipped IP	Cortex-A57, Cortex-M3, ARM926, DDR3L/4, USB2.0H, USB3.0H,USB3.0D,PCIe, SATA, SD, BbyOne, ADC, GEtherMac,GPU
development period
	About 1.5 months
Job Description
	We provide a verification environment that meets the needs of our customers, including a verification environment using models and shorter TATs. 〇It is possible to replace the installed IP such as CPU with the bus model. It has the following benefits 〇It is possible to perform simple verification of bus access without knowing about IP. 〇By changing to a model, the CPU execution load of the simulation can be reduced. 〇Total management from SIM execution to result confirmation by supporting vMavager (Cadence).

Front-end design example 2

Business Overview
	Customers	Domestic semiconductor manufacturers
	End customers	Domestic set manufacturers
	Business form	Design by contract
	Scope of work	Third-party verification of Communications IP
development period
	About 3 months
Job Description
	Formal verification was applied to the entire IP a third party’s perspective while referring to the circuit design specifications and the programming manuals. Quality Application of exhaustive verification methods using formal verification tools Cost Create assertions for validation (versatility) on deployed products Delivery Effective use of JasperGold apps to improve verification efficiency

Front-end design example 3

Business Overview
	Customers	Domestic semiconductor manufacturers
	End customers	Domestic set manufacturers
	Business form	Design by contract
	Scope of work	Chip functional verification
Product Overview
	Process	40nm
	Equipped IP	Cortex-A9, ARM926, DDR2/3, USB3.0D, Serdes, SD, GEtherMac
development period
	About 3 months
Job Description
	We have built a chip total simulation environment and performed logical verification by fusing the operating program created by a domestic set manufacturer and the operating program created by an on-board IP development manufacturer. Create a verification environment that absorbs the differences in scenario formats provided by customers.

Back-end design example

Back-end design example 1

Job Description

Development of digital part of integrated chip for analog-digital mixed

- Obtain RTL of digital part, and design and verification of the entire process from logic synthesis to GDS.
- Layout verification after merging of analog and digital sections.

Challenges in development

- FAB & process that are handled for the first time
- Design and verification using expensive tools
- Tool license borrowing for a period of time to reduce costs (tool use limited)
- Short TAT development (about 3 weeks, including trial)

Results and Our Advantage

Minimized costs and completed development on time

〇Multi-Fab Design House. (can be designed with any FAB or process)

- Maximizing FAB performance with techniques that immediately understand design rules and process model features.

〇Mastering new inexpensive tools in a short period of time.

- Since we have a clear design policy and target, we don’t create a backward process by confirming the tool characteristics in advance.

〇Development completed with short TAT.

- Create QA sheets, and carefully share design details and input data information with customers. Identify difficult issues and important design points in advance and prepare risk hedging and countermeasures in advance.
- Understand circuit configuration from conventional product data, Reading circuit information from design data and providing high performance products with additional technology.

Back-end design example 2

Business Overview
	Customers	Overseas semiconductor manufacturers
	End customers	Domestic set manufacturers
	Business form	Design outsourcing services
	Scope of work	Design and verification from gate netlist to GDS creation
Product Overview
	Process	55nm
	Circuit scale	4M Gate
	Equipped IP	DDR3, PCI-Express, LVDS, PLL
	Special note	Fault coverage of 99.8% or more
development period
	Trial Typically, we obtain dirty file data from the customer to do a trial design. The purpose of the trial is to confirm the feasibility and eliminate the problems for the production, and to design and verify the same as the production. The trial period and the start of the trial will be decided by consulting with the customer, depending on the release date of the final data and the accuracy of the dirty file. Final The entire process for this product was completed in 1.5 months on schedule. Various quality checks such as policy reviews, design reviews, and shipping audits were also conducted at each design process.
Job Description
	DFT 99.8% Fault coverage achieved with minimal increase in circuit size Quickly extract issues at the start of the design. Understanding the circuit configuration and the difficulty level of countermeasures, Identify the trends in the circuit configuration of commercial tools (mainly SCAN) and in-house tools (TEST clock and RAM BIST), and insert CLK/RST control and fault detection circuits by our own method.
	STA One step further analysis and support Improved timing library problems for new IPs, Propose a library based on circuit configuration and IP behavior (characterization conditions such as clock and data pin relationships) Proposed improvements to timing paths that are not feasible, Where there was a problem with timing constraints, the timing margin that should have been there was confirmed, and the problem was extracted. Support for the creation of timing constraints for domestic end customers, In order to realize the specifications originally intended, we provide direct support to the end customer by proposing specific methods of describing the constraints.
	LAYOUT Chip size reduction through optimization, including IO planning In order to minimize the chip size, it is essential to optimize not only the floor plan but also the number of power supplies and IO and IP placement position adjustment. In this product, the chip size has been reduced, including these optimizations. State-of-the-art verification and optimization techniques In the IR-Drop verification, not only Static but also Dynamic verification is performed. It is also done in SCAN Shift mode, which has become a problem in recent years. Improved the quality of Power Integrity by eliminating high-resistance power wiring and inserting proper decoupling.
	ES delivery Both the wafer test and the final test had no problems, and the ES was able to run in one shot.

FPGA Design Examples

FPGA design examples (1)

Business Overview

	Customers	Domestic set manufacturers
	Business form	Design outsourcing services
	Scope of work	FPGA compilation and layout work for designs that are having difficulty with timing closure.
Product Overview
	Specifications and Devices	Xilinx Kintex UltraScale(20nm)KU115
	FPGA scale	1451K System Logic Cells
	Macros on board	DDR4(222MHz), Aurora(148MHz), AXI(148MHz)
	Special note	Final result：No timing error, compile time (synthesis + imprint) within 12 hours
development period
	About 1 month
Job Description
	We contribute to the realization of high-performance image processing systems by maximizing the performance of high-end FPGAs with our strength in large-scale, high-speed design layout technology. The shortest way to solve a problem is to find out the cause of the problem “quickly, correctly and concretely”. If the cause is clarified, we have the soil groundwork to create ideas for countermeasures.